High performance 14nm SOI FinFET CMOS technology with 0.0174μm2 embedded DRAM and 15 levels of Cu metallization
- C.-H.C-H. Lin
- Brian Greene
- et al.
- 2014
- IEDM 2014
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20 results for S.-J. Jeng
High performance 45-nm SOI technology with enhanced strain, porous low-k BEOL, and immersion lithography
- S. Narasimha
- K. Onishi
- et al.
- 2006
- IEDM 2006
SiGe HBT technology with f max/f T = 350/300 GHz and gate delay below 3.3 ps
- M. Khater
- J.-S. Rieh
- et al.
- 2004
- IEDM 2004
Manufacturability demonstration of an integrated SiGe HBT technology for the analog and wireless marketplace
- D. Ahlgren
- M.M. Gilbert
- et al.
- 1996
- IEDM 1996
200 mm SiGe-HBT technology for wireless and mixed-signal applications
- D.L. Harame
- K. Schonenberg
- et al.
- 1994
- IEDM 1994
Self-aligned SiGe NPN transistors with 285 GHz f MAX and 207 GHz f T in a manufacturable technology
- B. Jagannathan
- M. Khater
- et al.
- 2002
- IEEE Electron Device Letters
Yield monitor for embedded-SiGe process optimization
- Xu Ouyang
- Shwu-Jen Jeng
- et al.
- 2008
- ICSICT 2008
Hole transport in nanoscale p-type MOSFET SOI devices with high strain
- H. Nayfeh
- S.-J. Jeng
- et al.
- 2007
- DRC 2007
Pushing the performance limits of SiGe HBT technology
- Marwan Khater
- Thomas Adam
- et al.
- 2006
- ECS Meeting 2006
SiGe HBTs for millimeter-wave applications with simultaneously optimized f T and f max of 300 GHz
- J.-S. Rieh
- D.R. Greenberg
- et al.
- 2004
- RFIC 2004