High performance 14nm SOI FinFET CMOS technology with 0.0174μm2 embedded DRAM and 15 levels of Cu metallization
- C.-H.C-H. Lin
- Brian Greene
- et al.
- 2014
- IEDM 2014
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High performance bulk planar 20nm CMOS technology for low power mobile applications
- Huiling Shang
- Sameer Jain
- et al.
- 2012
- VLSI Technology 2012
Characterization of silicide-silicon interface contact resistivity using 1-D dual transmission line model approximation of modified cross bridge kelvin measurements
- Ankur Arya
- Balaji Jayaraman
- et al.
- 2011
- IWPSD 2011