Replacement metal gate resistance in FinFET architecture modelling, validation and extendibility
- Ruqiang Bao
- Brian Greene
- et al.
- 2015
- IEDM 2015
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14 results for Chung-Hsun Lin
Challenges and solutions of FinFET integration in an SRAM cell and a logic circuit for 22 nm node and beyond
- H. Kawasaki
- V.S. Basker
- et al.
- 2009
- IEDM 2009
Extraction of effective oxide thickness for SOI FINFETs with high-κ/Metal gates using the body effect
- Sujata Paul
- Frank Yeh
- et al.
- 2010
- IEEE Electron Device Letters
A comparative study of fin-last and fin-first SOI FinFETs
- Darsen Lu
- Josephine Chang
- et al.
- 2013
- SISPAD 2013
Channel doping impact on FinFETs for 22nm and beyond
- Chung-Hsun Lin
- R. Kambhampati
- et al.
- 2012
- VLSI Technology 2012
Modeling of width-quantization-induced variations in logic FinFETs for 22nm and beyond
- Chung-Hsun Lin
- Wilfried Haensch
- et al.
- 2011
- VLSI Technology 2011
Non-planar device architecture for 15nm node: FinFET or trigate?
- Chung-Hsun Lin
- Josephine Chang
- et al.
- 2010
- IEEE International SOI Conference 2010
Hot-carrier degradation in undoped-body etsoi fets and soi finfets
- Miaomiao Wang
- Pranita Kulkarni
- et al.
- 2010
- IRPS 2010
FinFET resistance mitigation through design and process optimization
- Cindy Wang
- Josephine Chang
- et al.
- 2009
- VLSI-TSA 2009
VDD scaling for FinFET logic and memory circuits: The impact of process variations and SRAM stability
- C.-H. Lin
- K. Das
- et al.
- 2006
- VLSI-TSA 2006