Predictive Guardbanding: Program-Driven Timing Margin Reduction for GPUsJingwen LengAlper Buyuktosunogluet al.2021IEEE TCADIS
The POWER Processor Family: A Historical Perspective from the Viewpoint of Presilicon ModelingPradip Bose2021IEEE Micro
Asymmetric resilience: Exploiting task-level idempotency for transient error recovery in accelerator-based systemsJingwen LengAlper Buyuktosunogluet al.2020HPCA 2020
(Invited) cross-layer resilience: Challenges, insights, and the road aheadEric ChengDaniel Mueller-Gritschnederet al.2019DAC 2019
Generation of Stressmarks for Early Stage Soft-Error ModelingKarthik SwaminathanRamon Bertranet al.2019DSN-S 2019
Resilient low voltage accelerators for high energy efficiencyNandhini ChandramoorthyKarthik Swaminathanet al.2019HPCA 2019
Asymmetric Resilience for Accelerator-Rich SystemsJingwen LengAlper Buyuktosunogluet al.2019IEEE Computer Architecture Letters
ChopStiX: Systematic Extraction of Code-Representative MicrobenchmarksCalvin BullaLluc Alvarezet al.2018IISWC 2018
Towards 'Smarter' Vehicles Through Cloud-Backed Swarm CognitionAugusto VegaAlper Buyuktosunogluet al.2018IV 2018
Tolerating soft errors in processor cores using CLEAR (cross-layer exploration for architecting resilience)Eric ChengShahrzad Mirkhaniet al.2018IEEE TCADIS