SMT malleability in IBM POWER5 and POWER6 processors
- Alessandro Morari
- Carlos Boneti
- et al.
- 2013
- IEEE TC
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132 results for Pradip Bose
Integrated analysis of power and performance for pipelined microprocessors
- Victor Zyuban
- David Brooks
- et al.
- 2004
- IEEE TC
A Novel Technique for Efficient Parallel Implementation of a Classical Logic/ Fault Simulation Problem
- Pradip Bose
- 1988
- IEEE TC
A scalable methodology for agile chip development with open-source hardware components
- Maico Cassel Dos Santos
- Tianyu Jia
- et al.
- 2022
- ICCAD 2022
Measurement-Driven Methodology for Evaluating Processor Heterogeneity Options for Power-Performance Efficiency
- William J. Song
- Alper Buyuktosunoglu
- et al.
- 2016
- ISLPED 2016
A 12nm Agile-Designed SoC for Swarm-Based Perception with Heterogeneous IP Blocks, a Reconfigurable Memory Hierarchy, and an 800MHz Multi-Plane NoC
- Tianyu Jia
- Paolo Mantovani
- et al.
- 2022
- ESSCIRC 2022
SERMiner : A Framework for Early-stage Reliability Estimation for IBM Processors
- 2021
- DSN-S 2021
MicroGrad: A Centralized Framework for Workload Cloning and Stress Testing
- Gokul Subramanian Ravi
- Ramon Bertran
- et al.
- 2021
- ISPASS 2021
Asymmetric resilience: Exploiting task-level idempotency for transient error recovery in accelerator-based systems
- Jingwen Leng
- Alper Buyuktosunoglu
- et al.
- 2020
- HPCA 2020
Generation of Stressmarks for Early Stage Soft-Error Modeling
- 2019
- DSN-S 2019