Generation of Stressmarks for Early Stage Soft-Error ModelingKarthik SwaminathanRamon Bertranet al.2019DSN-S 2019
Resilient low voltage accelerators for high energy efficiencyNandhini ChandramoorthyKarthik Swaminathanet al.2019HPCA 2019
Asymmetric Resilience for Accelerator-Rich SystemsJingwen LengAlper Buyuktosunogluet al.2019IEEE Computer Architecture Letters
ChopStiX: Systematic Extraction of Code-Representative MicrobenchmarksCalvin BullaLluc Alvarezet al.2018IISWC 2018
Towards 'Smarter' Vehicles Through Cloud-Backed Swarm CognitionAugusto VegaAlper Buyuktosunogluet al.2018IV 2018
Tolerating soft errors in processor cores using CLEAR (cross-layer exploration for architecting resilience)Eric ChengShahrzad Mirkhaniet al.2018IEEE TCADIS
Impact of software approximations on the resiliency of a video summarization systemRadha VenkatagiriKarthik Swaminathanet al.2018DSN 2018
DyHard-DNN: Even more DNN acceleration with dynamic hardware reconfigurationMateja PuticAlper Buyuktosunogluet al.2018DAC 2018