Publications

8 results for John C Arnold

NanoStack Transistor Architecture for CMOS 7A Node and Beyond
- - Shay Reboh
  - Chen Zhang
  - et al.
- 2025
- VLSI Technology and Circuits 2025
Fully subtractive Ru Topvia interconnects with minimum 9 nm-space airgap for RC performance and reliability enhancement as post-Cu interconnects
- - Koichi Motoyama
  - Jaemyung Choi
  - et al.
- 2024
- IEDM 2024
Monolithic Stacked FET with Stepped Channels for Future Logic Technologies
- - Chen Zhang
  - Seungmin Song
  - et al.
- 2024
- IEDM 2024
Backside power distribution for nanosheet technologies beyond 2nm
- - Ruilong Xie
  - Wonhyuk Hong
  - et al.
- 2024
- VLSI Technology and Circuits 2024
Plasma Processing and the Semiconductor Supply Chain in an Era of Low GWP and/or PFAS-Free Gas Chemistries
- - Eric A. Joseph
  - Brooke Tvermoes
  - et al.
- 2024
- CMC Conference 2024
EUV Double Patterning Solution for Subtractive Metal Patterning at 18nm Pitch
- - Chris Penny
  - Koichi Motoyama
  - et al.
- 2024
- SPIE Advanced Lithography + Patterning 2024
Etch and Patterning Development for 2nm Node Nanosheet Devices
- - Eric Miller
  - Indira Seshadri
  - et al.
- 2022
- SPIE Advanced Lithography 2022
Exploration of pillar local CDU improvement options for AI applications
- - Charlie Liu
  - Hao Tang
  - et al.
- 2020
- SPIE Advanced Lithography 2020