Eliminating Redundancy: Ultra-compact Code Generation for Programmable Dataflow Accelerators
- Prasanth Chatarasi
- Alex Gatea
- et al.
- 2026
- CGO 2026
Publications
63 results for Vijayalakshmi Srinivasan
Enabling Spill-Free Compilation via Affine-Based Live Range Reduction Optimization
- Prasanth Chatarasi
- Alex Gatea
- et al.
- 2026
- CGO 2026
Enabling Enterprise AI with IBM Spyre
- Jeffrey Burns
- Leland Chang
- et al.
- 2025
- IEDM 2025
A Software-Assisted Peak Current Regulation Scheme to Improve Power-Limited Inference Performance in a 5nm AI SoC
- Monodeep Kar
- Joel Silberman
- et al.
- 2024
- ISSCC 2024
Power-Limited Inference Performance Optimization Using a Software-Assisted Peak Current Regulation Scheme in a 5-nm AI SoC
- Monodeep Kar
- Joel Silberman
- et al.
- 2024
- IEEE Journal of Solid-State Circuits
DNNDaSher: A Compiler Framework for Dataflow Compatible End-to-End Acceleration on IBM AIU
- Sanchari Sen
- Shubham Jain
- et al.
- 2024
- IEEE Micro
Deep Compression of Pre-trained Transformer Models
- Naigang Wang
- Chi-Chun Liu
- et al.
- 2022
- NeurIPS 2022
OnSRAM: Efficient Inter-Node On-Chip Scratchpad Management in Deep Learning Accelerators
- Subhankar Pal
- Swagath Venkataramani
- et al.
- 2022
- Transactions on Embedded Computing Systems
A 7-nm Four-Core Mixed-Precision AI Chip with 26.2-TFLOPS Hybrid-FP8 Training, 104.9-TOPS INT4 Inference, and Workload-Aware Throttling
- Sae Kyu Lee
- Ankur Agrawal
- et al.
- 2021
- IEEE JSSC
RaPiD: AI Accelerator for Ultra-Low Precision Training and Inference
- Swagath Venkataramani
- Vijayalakshmi Srinivasan
- et al.
- 2021
- ISCA 2021