Characterization of stacked die using die-to-wafer integration for high yield and throughput
- K. Sakuma
- P. Andry
- et al.
- 2008
- ECTC 2008
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55 results for Paul Andry
3D chip-stacking technology with through-silicon vias and low-volume lead free interconnections
- Katsuyuki Sakuma
- Paul S. Andry
- et al.
- 2008
- IBM J. Res. Dev
Fabrication and characterization of robust through-silicon vias for silicon-carrier applications
- Paul S. Andry
- Cornelia K. Tsang
- et al.
- 2008
- IBM J. Res. Dev
3D chip stacking with C4 technology
- Bing Dang
- Steven L. Wright
- et al.
- 2008
- IBM J. Res. Dev
Three-dimensional silicon integration
- John U. Knickerbocker
- Paul S. Andry
- et al.
- 2008
- IBM J. Res. Dev
Assembly, characterization, and reworkability of Pb-free ultra-fine pitch C4s for system-on-package
- B. Dang
- S.L. Wright
- et al.
- 2007
- ECTC 2007
3D chip stacking technology with low-volume lead-free interconnections
- K. Sakuma
- P. Andry
- et al.
- 2007
- ECTC 2007
Interconnects in the third dimension: Design challenges for 3D ICs
- Kerry Bernstein
- Paul Andry
- et al.
- 2007
- DAC 2007
CMOS-compatible through silicon vias for 3D process integration
- Cornelia K. Tsang
- Paul S. Andry
- et al.
- 2006
- MRS Fall Meeting 2006
A CMOS-compatible process for fabricating electrical through-vias in silicon
- P. Andry
- C. Tsang
- et al.
- 2006
- ECTC 2006