Chidanand Apté, Fred Damerau, et al.
ACM Transactions on Information Systems (TOIS)
Three-dimensional (3D) integration technology promises to continue enhancing integrated-circuit system performance with high bandwidth, low latency, low power, and a small form factor for a variety of applications. In this work, conventional C4 (controlled-collapse chip connection) technology is studied for robust interconnection between stacked thin chips. Various solder hierarchies to enable 3D chip stacking and packaging are investigated. Examples are presented to compare stacking schemes with sequential and parallel reflow. Chips as thin as 90 μm are stacked using conventional chip-placement and reflow processes, and the associated process challenges are investigated and discussed. Warpage of the thin chips is measured on various substrates. Rework of the chip stack has also been demonstrated through a temporary chip attachment operation, and the scalability of reworkable C4 is investigated. © Copyright 2008 by International Business Machines Corporation.
Chidanand Apté, Fred Damerau, et al.
ACM Transactions on Information Systems (TOIS)
Raghu Krishnapuram, Krishna Kummamuru
IFSA 2003
Liat Ein-Dor, Y. Goldschmidt, et al.
IBM J. Res. Dev
Kafai Lai, Alan E. Rosenbluth, et al.
SPIE Advanced Lithography 2007