A 6.0-mW 10.0-Gb/s receiver with switched-capacitor summation DFE
- Azita Emami-Neyestanak
- Aida Varzaghani
- et al.
- 2007
- IEEE Journal of Solid-State Circuits
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69 results for Daniel Friedman
All-digital dynamic self-detection and self-compensation of static phase offsets in charge-pump PLLs
- Liu Yong
- Woogeun Rhee
- et al.
- 2007
- ISSCC 2007
A 7Gb/s 9.3mW 2-Tap current-integrating DFE receiver
- Matt Park
- John Bulzacchelli
- et al.
- 2007
- ISSCC 2007
A wide power-supply range (0.5V-to-1.3V) wide tuning range (500 MHz-to-8 GHz) all-static CMOS AD PLL in 65nm SOI
- A. Rylyakov
- J. Tierno
- et al.
- 2007
- ISSCC 2007
A 10-Gb/s 5-tap DFE/4-tap FFE transceiver in 90-nm CMOS technology
- John F. Bulzacchelli
- Mounir Meghelli
- et al.
- 2006
- IEEE Journal of Solid-State Circuits
An ultra compact differentially tuned 6 GHz CMOS LC VCO with dynamic common-mode feedback
- Babak Soltanian
- Herschel Ainspan
- et al.
- 2006
- CICC 2006
A 10Gb/s 5-tap-DFE/4-tap-FFE transceiver in 90nm CMOS
- M. Meghelli
- S. Rylov
- et al.
- 2006
- ISSCC 2006
A low-power receiver with switched-capacitor summation DFE
- Azita Emami-Neyestanak
- Aida Varzaghani
- et al.
- 2006
- VLSI Circuits 2006
Phase and amplitude pre-emphasis techniques for low-power serial links
- James F. Buckwalter
- Mounir Meghelli
- et al.
- 2006
- IEEE Journal of Solid-State Circuits
A Semi-Digital Delay-Locked Loop Using an Analog-Based Finite State Machine
- Woogeun Rhee
- Benjamin Parker
- et al.
- 2004
- IEEE TCAS-II