A single-chip 12.5Gbaud transceiver for serial data communication
- D. Friedman
- M. Meghelli
- et al.
- 2001
- VLSI Circuits 2001
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69 results for Daniel Friedman
Sub-picosecond jitter SiGe BiCMOS transmit and receive PLLs for 12.5 Gbaud serial data communication
- D. Friedman
- M. Meghelli
- et al.
- 2000
- VLSI Circuits 2000
Superconducting VLSI Logic Cell Library Using DC-Powered Clockless Dynamic SFQ Gates and ASIC-Style Layout Template
- Sergey Rylov
- Matthew Beck
- et al.
- 2023
- IEEE TAS
Indirect performance sensing for on-chip self-healing of analog and RF circuits
- Shupeng Sun
- Fa Wang
- et al.
- 2014
- IEEE TCAS-I
Adaptive circuit design methodology and test applied to millimeter-wave circuits
- Jean-Olivier Plouchart
- Benjamin Parker
- et al.
- 2014
- IEEE Design and Test
A 23.5 GHz PLL with an adaptively biased VCO in 32 nm SOI-CMOS
- Jean-Olivier Plouchart
- Mark A. Ferriss
- et al.
- 2013
- IEEE TCAS-I
Specifications of nanoscale devices and circuits for neuromorphic computational systems
- Bipin Rajendran
- Yong Liu
- et al.
- 2013
- IEEE T-ED
An 8x 10-Gb/s source-synchronous I/O system based on high-density silicon carrier interconnects
- Timothy O. Dickson
- Yong Liu
- et al.
- 2012
- IEEE Journal of Solid-State Circuits
Dual-loop system of distributed microregulators with high DC accuracy, load response time below 500 ps, and 85-mV dropout voltage
- John F. Bulzacchelli
- Zeynep Toprak-Deniz
- et al.
- 2012
- IEEE Journal of Solid-State Circuits
A 10-Gb/s compact low-power serial I/O with DFE-IIR equalization in 65-nm CMOS
- Byungsub Kim
- Yong Liu
- et al.
- 2009
- IEEE Journal of Solid-State Circuits