Chip-level power-performance optimization through thermally-driven across-chip variation (ACV) reduction
- X. Yu
- Oleg Gluschenkov
- et al.
- 2011
- IEDM 2011
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8 results for Jim Culp
Verification of untrusted chips using trusted layout and emission measurements
- Franco Stellari
- Peilin Song
- et al.
- 2014
- HOST 2014
MARVEL Malicious alteration recognition and verification by emission of light
- Peilin Song
- Franco Stellari
- et al.
- 2011
- HOST 2011
Compensating non-optical effects using electrically-driven optical proximity correction
- Shayak Banerjee
- Kanak B. Agarwal
- et al.
- 2009
- SPIE Advanced Lithography 2009
Layout Optimization at the pinnacle of Optical Lithography
- Lars Liebmann
- Greg Northrop
- et al.
- 2003
- SPIE Advanced Microelectronic Manufacturing 2003
High performance 0.13 μm SOI CMOS technology with Cu interconnects and low-k BEOL dielectric
- P. Smeys
- V. McGahay
- et al.
- 2000
- VLSI Technology 2000
Power optimization methodology for the IBM POWER7 microprocessor
- Victor V. Zyuban
- Joshua Friedrich
- et al.
- 2011
- IBM J. Res. Dev
Enabling the 70 nm technology node with 193 nm altPSM lithography
- Lars Liebmann
- Jennifer Lund
- et al.
- 2002
- Proceedings of SPIE-The International Society for Optical Engineering