A 500 MHz Random Cycle, 1.5 ns Latency, SOI Embedded DRAM Macro Featuring a Three-Transistor Micro Sense Amplifier
- John Barth
- William R. Reohr
- et al.
- 2008
- IEEE Journal of Solid-State Circuits
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1-GHz fully pipelined 3.7-ns address access time 8 k × 1024 embedded synchronous DRAM macro
- Osamu Takahashi
- Sang H. Dhong
- et al.
- 2000
- IEEE Journal of Solid-State Circuits