Bonding technologies for chip level and wafer level 3D integration
- Katsuyuki Sakuma
- Spyridon Skordas
- et al.
- 2014
- ECTC 2014
Publications
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22 results for Subramanian Iyer
3D copper TSV integration, testing and reliability
- Mukta Farooq
- T. Graves-Abe
- et al.
- 2011
- IEDM 2011
A 0.039um2 high performance eDRAM cell based on 32nm high-K/metal SOI technology
- Nauman Z. Butt
- Kevin McStay
- et al.
- 2010
- IEDM 2010
Scaling deep trench based eDRAM on SOI to 32nm and beyond
- G. Wang
- D. Anand
- et al.
- 2009
- IEDM 2009
A 500MHz random cycle 1.5ns-latency, SOI embedded DRAM macro featuring a 3T micro sense amplifier
- John Barth
- William Reohr
- et al.
- 2007
- ISSCC 2007
A 0.127 μm2 high performance 65 nm SOI based embedded DRAM for on-processor applications
- G. Wang
- K. Cheng
- et al.
- 2006
- IEDM 2006
Copper through silicon via (TSV) for 3D integration
- C. Kothandaraman
- B. Himmel
- et al.
- 2012
- IRPS 2012
Performance analysis and modeling of deep trench decoupling capacitor for 32 nm high-performance SOI processors and beyond
- Balaji Jayaraman
- Sneha Gupta
- et al.
- 2012
- ICICDT 2012
Three dimensional integration - Memory applications
- S.S. Iyer
- 2009
- IEEE International SOI Conference 2009
Process-design considerations for three dimensional memory integration
- S.S. Iyer
- T. Kirihata
- et al.
- 2009
- VLSI Technology 2009