Publications

22 results for Subramanian Iyer

Bonding technologies for chip level and wafer level 3D integration
- - Katsuyuki Sakuma
  - Spyridon Skordas
  - et al.
- 2014
- ECTC 2014
Modeling and characterization of gate leakage in high-K metal gate technology-Based embedded DRAM
- - Mohit Bajaj
  - Rajan K. Pandey
  - et al.
- 2013
- IEEE T-ED
Copper through silicon via (TSV) for 3D integration
- - C. Kothandaraman
  - B. Himmel
  - et al.
- 2012
- IRPS 2012
Performance analysis and modeling of deep trench decoupling capacitor for 32 nm high-performance SOI processors and beyond
- - Balaji Jayaraman
  - Sneha Gupta
  - et al.
- 2012
- ICICDT 2012
3D copper TSV integration, testing and reliability
- - Mukta Farooq
  - T. Graves-Abe
  - et al.
- 2011
- IEDM 2011
3D integration review
- - Mukta G. Farooq
  - Subramanian S. Iyer
- 2011
- Science China Information Sciences
A 0.039um² high performance eDRAM cell based on 32nm high-K/metal SOI technology
- - Nauman Z. Butt
  - Kevin McStay
  - et al.
- 2010
- IEDM 2010
Three dimensional integration - Memory applications
- - S.S. Iyer
- 2009
- IEEE International SOI Conference 2009
Scaling deep trench based eDRAM on SOI to 32nm and beyond
- - G. Wang
  - D. Anand
  - et al.
- 2009
- IEDM 2009
Process-design considerations for three dimensional memory integration
- - S.S. Iyer
  - T. Kirihata
  - et al.
- 2009
- VLSI Technology 2009