SiGe FinFET for practical logic libraries by mitigating local layout effect
- G. Tsutsui
- Huimei Zhou
- et al.
- 2017
- VLSI Technology 2017
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15 results for Eric Miller
Technology viable DC performance elements for Si/SiGe channel CMOS FinFTT
- G. Tsutsui
- Ruqiang Bao
- et al.
- 2016
- IEDM 2016
A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels
- Ruilong Xie
- Pietro Montanini
- et al.
- 2016
- IEDM 2016
Advanced in-line metrology strategy for self-aligned quadruple patterning
- Robin Chao
- Mary Breton
- et al.
- 2016
- SPIE Advanced Lithography 2016
EUV patterning successes and frontiers
- Nelson Felix
- Daniel Corliss
- et al.
- 2016
- SPIE Advanced Lithography 2016