Scaling opportunities for Gate-All-Around: A patterning perspective
- I. Seshadri
- E. Miller
- et al.
- 2023
- IEDM 2023
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13 results for Eric Miller
Functional Testing of AI Cores through Thinned 3D I/O Buffer Dies in 3D Die-Stacked Modules
- Mukta Farooq
- Arvind Kumar
- et al.
- 2022
- ECTC 2022
Vertical-Transport Nanosheet Technology for CMOS Scaling beyond Lateral-Transport Devices
- H. Jagannathan
- B. Anderson
- et al.
- 2021
- IEDM 2021
Technology viable DC performance elements for Si/SiGe channel CMOS FinFTT
- G. Tsutsui
- Ruqiang Bao
- et al.
- 2016
- IEDM 2016
A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels
- Ruilong Xie
- Pietro Montanini
- et al.
- 2016
- IEDM 2016
Contact local CD uniformity optimization through etch shrink
- Eric Miller
- Junling Sun
- et al.
- 2021
- SPIE Advanced Lithography 2021
Fundamental characterization of stochastic variation for improved single-expose EUV patterning at aggressive pitch
- Jennifer Church
- Luciana Meli
- et al.
- 2020
- SPIE Advanced Lithography 2020
SiGe FinFET for practical logic libraries by mitigating local layout effect
- G. Tsutsui
- Huimei Zhou
- et al.
- 2017
- VLSI Technology 2017
EUV patterning successes and frontiers
- Nelson Felix
- Daniel Corliss
- et al.
- 2016
- SPIE Advanced Lithography 2016
Advanced in-line metrology strategy for self-aligned quadruple patterning
- Robin Chao
- Mary Breton
- et al.
- 2016
- SPIE Advanced Lithography 2016