Spacer-defined double patterning for 20-nm and beyond logic BEOL technology
- Ryoung-Han Kim
- Chiew-Seng Koay
- et al.
- 2011
- SPIE Advanced Lithography 2011
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22 results for S. Mehta
Extremely thin SOI (ETSOI) technology: Past, present, and future
- Kangguo Cheng
- A. Khakifirooz
- et al.
- 2010
- IEEE International SOI Conference 2010
Challenges and opportunities of extremely thin SOI (ETSOI) CMOS technology for future low power and general purpose system-on-chip applications
- A. Khakifirooz
- Kangguo Cheng
- et al.
- 2010
- VLSI-TSA 2010
Ultra-thin-body and BOX (UTBB) Fully Depleted (FD) device integration for 22nm node and beyond
- Q. Liu
- A. Yagishita
- et al.
- 2010
- VLSI Technology 2010
Spacer defined double patterning for sub-72 nm pitch logic technology
- Ryoung-Han Kim
- Erin McLellan
- et al.
- 2010
- SPIE Advanced Lithography 2010
Extremely thin SOI (ETSOI) CMOS with record low variability for low power system-on-chip applications
- K. Cheng
- A. Khakifirooz
- et al.
- 2009
- IEDM 2009
Copper contact metallization using Ru-based barrier liners for 45 nm and 32 nm nodes: Reliability and device performance
- Soon-Cheon Seo
- Chih-Chao Yang
- et al.
- 2008
- ADMETA 2008
Copper contact metallization for 22 nm and beyond
- Soon-Cheon Seo
- Chih-Chao Yang
- et al.
- 2009
- IITC 2009
22 nm technology compatible fully functional 0.1 μm 2 6T-sram cell
- B. Haran
- A. Kumar
- et al.
- 2008
- IEDM 2008
A 45 nm CMOS node Cu/low-k/ ULtra low-k PECVD SiCOH (k=2.4) BEOL technology
- S. Sankaran
- S. Arai
- et al.
- 2006
- IEDM 2006