Electronic and structural analysis of ultra-small-diameter metal disilicide nanowires
- Nicholas A. Lanzillo
- T. Standaert
- et al.
- 2017
- Journal of Applied Physics
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53 results for T. Standaert
A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels
- Ruilong Xie
- Pietro Montanini
- et al.
- 2016
- IEDM 2016
Via resistance reduction in advanced copper interconnects
- Chih-Chao Yang
- Terry A. Spooner
- et al.
- 2017
- IEEE Electron Device Letters
Post porosity plasma protection integration at 48 nm pitch
- H. Huang
- Krystelle Lionti
- et al.
- 2016
- IITC/AMC 2016
Pre-liner dielectric nitridation for resistance reduction in copper interconnects
- Chih-Chao Yang
- Terry A. Spooner
- et al.
- 2016
- IITC/AMC 2016
Interconnect performance and scaling strategy at the 5 nm Node
- James H.-C. Chen
- N.V. Licausi
- et al.
- 2016
- IITC/AMC 2016
BEOL process integration for the 7 nm technology node
- T. Standaert
- Genevieve Beique
- et al.
- 2016
- IITC/AMC 2016
Si nanowire CMOS fabricated with minimal deviation from RMG FinFET technology showing record performance
- Isaac Lauer
- Nicolas Loubet
- et al.
- 2015
- VLSI Technology 2015
Through-Cobalt Self Forming Barrier (tCoSFB) for Cu/ULK BEOL: A novel concept for advanced technology nodes
- Takeshi Nogami
- Benjamin D. Briggs
- et al.
- 2015
- IEDM 2015
Bottom oxidation through STI (BOTS) - A novel approach to fabricate dielectric isolated FinFETs on bulk substrates
- K. Cheng
- S.-C. Seo
- et al.
- 2014
- VLSI Technology 2014