Future of plasma etching for microelectronics: Challenges and opportunities
- Gottlieb S. Oehrlein
- Stephan M. Brandstadter
- et al.
- 2024
- Journal of Vacuum Science and Technology B
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53 results for T. Standaert
A 14 nm embedded STT-MRAM CMOS technology
- Daniel C. Edelstein
- M. Rizzolo
- et al.
- 2020
- IEDM 2020
Novel low k Dielectric materials for nano device interconnect technology
- Son Van Nguyen
- Hosadurga Shobha
- et al.
- 2020
- VLSI-TSA 2020
Exploring the Limits of Cobalt Liner Thickness in Advanced Copper Interconnects
- Nicholas A. Lanzillo
- Kisik Choi
- et al.
- 2019
- IEEE Electron Device Letters
Technology challenges and enablers to extend Cu metallization to beyond 7 nm node
- Takeshi Nogami
- H. Huang
- et al.
- 2019
- VLSI Technology 2019
Electron Transport Across Cu/Ta(O)/Ru(O)/Cu Interfaces in Advanced Vertical Interconnects
- Nicholas A. Lanzillo
- Benjamin D. Briggs
- et al.
- 2019
- Computational Materials Science
Ru Liner Scaling with ALD TaN Barrier Process for Low Resistance 7 nm Cu Interconnects and beyond
- Koichi Motoyama
- O. Van Der Straten
- et al.
- 2018
- IITC 2018
Impact of Liner Metals on Copper Resistivity at beyond 7nm Dimensions
- H. Huang
- Nicholas A. Lanzillo
- et al.
- 2018
- IITC 2018
A Study on SADP Process Refresh for Patterning Correction
- James H.-C. Chen
- Isabel C Estrada-Raygoza
- et al.
- 2018
- IITC 2018
Process Challenges in Fully Aligned Via Integration for sub 32 nm Pitch BEOL
- Benjamin D. Briggs
- C.B. Pcethala
- et al.
- 2018
- IITC 2018