Sub-25nm FinFET with advanced fin formation and short channel effect engineering
- Tenko Yamashita
- Veeraraghvan S. Basker
- et al.
- 2011
- VLSI Technology 2011
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53 results for T. Standaert
ETSOI CMOS for system-on-chip applications featuring 22nm gate length, sub-100nm gate pitch, and 0.08μm2 SRAM cell
- Kangguo Cheng
- A. Khakifirooz
- et al.
- 2011
- VLSI Technology 2011
Opportunities and challenges of FinFET as a device structure candidate for 14nm node CMOS technology
- Tenko Yamashita
- Veeraraghvan S. Basker
- et al.
- 2011
- CSTIC 2011
Aggressively scaled strained-silicon-on-insulator undoped-body High-κ/Metal-Gate nFinFETs for high-performance logic applications
- Kingsuk Maitra
- Ali Khakifirooz
- et al.
- 2011
- IEEE Electron Device Letters
A 0.063 μm2 FinFET SRAM cell demonstration with conventional lithography using a novel integration scheme with aggressively scaled fin and gate pitch
- Veeraraghvan S. Basker
- Theodorus E. Standaert
- et al.
- 2010
- VLSI Technology 2010
Application of the short-pulse propagation technique for broadband characterization of PCB and other interconnect technologies
- Alina Deutsch
- Roger S. Krabbenhoft
- et al.
- 2010
- IEEE Trans Electromagn Compat
A multilevel copper/low-k/airgap BEOL technology
- S.V. Nitta
- S. Ponoth
- et al.
- 2007
- ADMETA 2007
Performance and reliability of airgaps for advanced BEOL Interconnects
- S.V. Nitta
- D. Edelstein
- et al.
- 2008
- IITC 2008
Evaluation of Cu CMP barrier slurries for Ultra Low-k dielectric film (k~2.4) for 45nm technology
- Feng Zhao
- Laertis Economikos
- et al.
- 2007
- ICPT 2007
Characterization, Modeling and Extraction of Cu Wire Resistance for 65 nm Technology
- Ning Lu
- M. Angyal
- et al.
- 2007
- CICC 2007