Double spin-torque magnetic tunnel junction devices for last-level cache applications
- G. Hu
- C. Safranski
- et al.
- 2022
- IEDM 2022
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48 results for S. L. Brown
Reliable Sub-nanosecond MRAM with Double Spin-torque Magnetic Tunnel Junctions
- C. Safranski
- G. Hu
- et al.
- 2022
- VLSI Technology and Circuits 2022
Demonstration of narrow switching distributions in STT-MRAM arrays for LLC applications at 1x nm node
- E. R.J. Edwards
- Guohan Hu
- et al.
- 2020
- IEDM 2020
Spin-transfer torque MRAM with reliable 2 ns writing for last level cache applications
- Guohan Hu
- D. Kim
- et al.
- 2019
- IEDM 2019
Key parameters affecting STT-MRAM switching efficiency and improved device performance of 400°C-compatible p-MTJs
- Guohan Hu
- M. G. Gottwald
- et al.
- 2017
- IEDM 2017
High-Q magnetic inductors for high efficiency on-chip power conversion
- Naigang Wang
- Bruce Doris
- et al.
- 2016
- IEDM 2016
STT-MRAM with double magnetic tunnel junctions
- Guohan Hu
- J.H. Lee
- et al.
- 2015
- IEDM 2015
Switching distributions and write reliability of perpendicular spin torque MRAM
- D.C. Worledge
- G. Hu
- et al.
- 2010
- IEDM 2010
Understanding mobility mechanisms in extremely scaled HfO2 (EOT 0.42 nm) using remote interfacial layer scavenging technique and V t-tuning dipoles with gate-first process
- T. Ando
- M.M. Frank
- et al.
- 2009
- IEDM 2009
Maximized benefit of LaAlO higher-κ gate dielectrics by optimizing the La/Al atomic ratio
- Hiroaki Arimura
- Stephen L. Brown
- et al.
- 2011
- IEEE Electron Device Letters