A 1 MB cache subsystem prototype with 1.8 ns embedded DRAMs in 45 nm SOI CMOS
- Peter J. Klim
- John Barth
- et al.
- 2009
- IEEE Journal of Solid-State Circuits
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13 results for Hillery C. Hunter
A 500 MHz Random Cycle, 1.5 ns Latency, SOI Embedded DRAM Macro Featuring a Three-Transistor Micro Sense Amplifier
- John Barth
- William R. Reohr
- et al.
- 2008
- IEEE Journal of Solid-State Circuits
An innovative low-power high-performance programmable signal processor for digital communications
- Jaime H. Moreno
- Victor Zyuban
- et al.
- 2003
- IBM J. Res. Dev