22nm High-performance SOI technology featuring dual-embedded stressors, Epi-Plate High-K deep-trench embedded DRAM and self-aligned Via 15LM BEOL
- S. Narasimha
- P. Chang
- et al.
- 2012
- IEDM 2012
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14 results for Rich Wise
High performance 45-nm SOI technology with enhanced strain, porous low-k BEOL, and immersion lithography
- S. Narasimha
- K. Onishi
- et al.
- 2006
- IEDM 2006
Dual stress liner for high performance sub-45nm gate length SOI CMOS manufacturing
- H.S. Yang
- R. Malik
- et al.
- 2004
- IEDM 2004
Advanced plasma etch technologies for nanopatterning
- Rich Wise
- 2012
- SPIE Advanced Lithography 2012
High-performance high-κ/metal gates for 45nm CMOS and beyond with gate-first processing
- M. Chudzik
- B. Doris
- et al.
- 2007
- VLSI Technology 2007
Patterning strategies for gate level tip-tip distance reduction in SRAM cell for 45nm and beyond
- Haoren Zhuang
- Helen Wang
- et al.
- 2007
- ISTC 2007
Thermally robust dual-work function ALD-MN x MOSFETs using conventional CMOS process flow
- D.-G. Park
- Z. Luo
- et al.
- 2004
- VLSI Technology 2004
Hardmask technology for sub-100 nm lithographic imaging
- Katherina Babich
- Arpan P. Mahorowala
- et al.
- 2003
- Microlithography 2003
Advanced plasma etch technologies for nanopatterning
- Rich Wise
- 2013
- J. Micro/Nanolithogr. MEMS MOEMS
Controlling line-edge roughness and reactive ion etch lag in sub-150 nm features in borophosphosilicate glass
- Parijat Bhatnagar
- Siddhartha Panda
- et al.
- 2007
- Journal of Applied Physics