Advanced plasma etch technologies for nanopatterning
- Rich Wise
- 2013
- J. Micro/Nanolithogr. MEMS MOEMS
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14 results for Rich Wise
22nm High-performance SOI technology featuring dual-embedded stressors, Epi-Plate High-K deep-trench embedded DRAM and self-aligned Via 15LM BEOL
- S. Narasimha
- P. Chang
- et al.
- 2012
- IEDM 2012
Advanced plasma etch technologies for nanopatterning
- Rich Wise
- 2012
- SPIE Advanced Lithography 2012
High-performance high-κ/metal gates for 45nm CMOS and beyond with gate-first processing
- M. Chudzik
- B. Doris
- et al.
- 2007
- VLSI Technology 2007
Controlling line-edge roughness and reactive ion etch lag in sub-150 nm features in borophosphosilicate glass
- Parijat Bhatnagar
- Siddhartha Panda
- et al.
- 2007
- Journal of Applied Physics
Patterning strategies for gate level tip-tip distance reduction in SRAM cell for 45nm and beyond
- Haoren Zhuang
- Helen Wang
- et al.
- 2007
- ISTC 2007
High performance 45-nm SOI technology with enhanced strain, porous low-k BEOL, and immersion lithography
- S. Narasimha
- K. Onishi
- et al.
- 2006
- IEDM 2006
Integrated non-SO 2 underlayer and improved line-edge-roughness dielectric etch process using 193 nm bilayer resist
- Parijat Bhatnagar
- Siddhartha Panda
- et al.
- 2006
- Applied Physics Letters
Etching silicon-containing bilayer resists in ammonia-based plasmas
- Siddhartha Panda
- Richard Wise
- et al.
- 2005
- Journal of Vacuum Science and Technology B: Microelectronics and Nanometer Structures
Dual stress liner for high performance sub-45nm gate length SOI CMOS manufacturing
- H.S. Yang
- R. Malik
- et al.
- 2004
- IEDM 2004