2nd Generation dual-channel optimization with cSiGe for 22nm HP technology and beyond
- C. Ortolland
- Daniel Jaeger
- et al.
- 2013
- IEDM 2013
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6 results for P. Chang
22nm High-performance SOI technology featuring dual-embedded stressors, Epi-Plate High-K deep-trench embedded DRAM and self-aligned Via 15LM BEOL
- S. Narasimha
- P. Chang
- et al.
- 2012
- IEDM 2012
Chip-level power-performance optimization through thermally-driven across-chip variation (ACV) reduction
- X. Yu
- Oleg Gluschenkov
- et al.
- 2011
- IEDM 2011
An anomalous correlation between gate leakage current and threshold voltage fluctuation in advanced MOSFETs
- Zihong Liu
- Paul Chang
- et al.
- 2010
- IEDM 2010
On the difference of temperature dependence of metal gate and poly gate SOI MOSFET threshold voltages
- Shu-Jen Han
- Xinlin Wang
- et al.
- 2008
- IEDM 2008
Reduction of RTA-driven intra-die variation via model-based layout optimization
- J.C. Scott
- O. Gluschenkov
- et al.
- 2009
- VLSI Technology 2009