22nm High-performance SOI technology featuring dual-embedded stressors, Epi-Plate High-K deep-trench embedded DRAM and self-aligned Via 15LM BEOL
- S. Narasimha
- P. Chang
- et al.
- 2012
- IEDM 2012
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17 results for G. Costrini
High performance 45-nm SOI technology with enhanced strain, porous low-k BEOL, and immersion lithography
- S. Narasimha
- K. Onishi
- et al.
- 2006
- IEDM 2006
22nm technology yield optimization using multivariate 3D virtual fabrication
- B. Cipriany
- B. Jagannathan
- et al.
- 2013
- SISPAD 2013
Electrical monitoring of gate and active area mask misalignment error
- Aditya Bansal
- Amith Singhee
- et al.
- 2011
- VLSI Circuits 2011
Addressable arrays implemented with one metal level for MOSFET and resistor variability characterization
- Mark B. Ketchen
- Manjul Bhushan
- et al.
- 2009
- ICMTS 2009
Investigation of CMOS devices with embedded SiGe source/drain on hybrid orientation substrates
- Qiqing Ouyang
- Min Yang
- et al.
- 2005
- VLSI Technology 2005
Dual stress liner enhancement in hybrid orientation technology
- C. Sheraw
- M. Yang
- et al.
- 2005
- VLSI Technology 2005
A 0.18μm Logic-based MRAM Technology for High Performance Nonvolatile Memory Applications
- A.R. Sitaram
- D.W. Abraham
- et al.
- 2003
- VLSI Technology 2003
Sub-micron platinum electrodes by through-mask plating
- K.L. Saenger
- G. Costrini
- et al.
- 2000
- ECS Meeting 2000
Electrodes and barriers for dram and feram: Processing, integration, and fundamentals
- K.L. Saenger
- P.C. Andricacos
- et al.
- 2001
- MRS Online Proceedings Library