Dual stress liner enhancement in hybrid orientation technologyC. SherawM. Yanget al.2005VLSI Technology 2005
High performance 65 nm SOI technology with enhanced transistor strain and advanced-low-K BEOLW.-H. LeeA. Waiteet al.2005IEDM 2005
Integration and optimization of embedded-SiGe, compressive and tensile stressed liner films, and stress memorization in advanced SOI CMOS technologiesM. HorstmannA. Weiet al.2005IEDM 2005
Stable SRAM cell design for the 32 nm node and beyondLeland ChangDavid M. Friedet al.2005VLSI Technology 2005
Looking into the crystal ball: Future device learning using hybrid E-beam and optical lithographyS.E. SteenS.J. McNabet al.2005Microlithography 2005
Aggressively scaled (0.143 μm 2) 6T-SRAM cell for the 32 nm node and beyondD. FriedJ. Hergenrotheret al.2004IEDM 2004
A Simplified Hybrid Orientation Technology (SHOT) for high performance CMOSB. DorisY. Zhanget al.2004VLSI Technology 2004
On the integration of CMOS with hybrid crystal orientationsM. YangV. Chanet al.2004VLSI Technology 2004