22nm High-performance SOI technology featuring dual-embedded stressors, Epi-Plate High-K deep-trench embedded DRAM and self-aligned Via 15LM BEOL
- S. Narasimha
- P. Chang
- et al.
- 2012
- IEDM 2012
Publications
Date
Featured collections
Popular topics
24 results for D. Fried
Challenges and opportunities for high performance 32 nm CMOS technology
- J. Sleight
- I. Lauer
- et al.
- 2006
- IEDM 2006
Integration and optimization of embedded-SiGe, compressive and tensile stressed liner films, and stress memorization in advanced SOI CMOS technologies
- M. Horstmann
- A. Wei
- et al.
- 2005
- IEDM 2005
High performance 65 nm SOI technology with enhanced transistor strain and advanced-low-K BEOL
- W.-H. Lee
- A. Waite
- et al.
- 2005
- IEDM 2005
Aggressively scaled (0.143 μm 2) 6T-SRAM cell for the 32 nm node and beyond
- D. Fried
- J. Hergenrother
- et al.
- 2004
- IEDM 2004
Metal-gate FinFET and fully-depleted SOI devices using total gate silicidation
- Jakub Kedzierski
- Edward Nowak
- et al.
- 2002
- IEDM 2002
A functional FinFET-DGCMOS SRAM cell
- E. Nowak
- B. Rainey
- et al.
- 2002
- IEDM 2002
22nm technology yield optimization using multivariate 3D virtual fabrication
- B. Cipriany
- B. Jagannathan
- et al.
- 2013
- SISPAD 2013
A simple hardware-based statistical model on 65nm SOI CMOS technology
- Q. Liang
- J.B. Johnson
- et al.
- 2007
- ISDRS 2007
SOI CMOS technology with 360GHz fT NFET, 260GHz fT PFET, and record circuit performance for millimeter-wave digital and analog system-on-chip applications
- Sungjae Lee
- Jonghae Kim
- et al.
- 2007
- VLSI Technology 2007