(110) Channel, SiON gate-dielectric PMOS with record high Ion=1 mA/μm through channel stress and source drain external resistance (R ext) engineering
- B. Yang
- A. Waite
- et al.
- 2007
- IEDM 2007
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63 results for Effendi Leobandung
Performance comparison and channel length scaling of strained Si FETs on SiGe-on-insulator (SGOI)
- J. Cai
- K. Rim
- et al.
- 2004
- IEDM 2004
Performance enhancement on sub-70 nm strained silicon SOI MOSFETS on ultra-thin thermally mixed strained silicon/SiGe on insulator(TM-SGOI) substrate with raised S/D
- B.H. Lee
- A.C. Mocuta
- et al.
- 2002
- IEDM 2002
High performance 0.18 μm SOI CMOS technology
- E. Leobandung
- E. Barth
- et al.
- 1999
- IEDM 1999
Scalability of SOI technology into 0.13 μm 1.2 V CMOS generation
- E. Leobandung
- M. Sherony
- et al.
- 1998
- IEDM 1998
7.9/5.5 psec room/low temperature SOI CMOS
- F. Assaderaghi
- W. Rausch
- et al.
- 1997
- IEDM 1997
0.25 μm CMOS SOI technology and its application to 4 Mb SRAM
- D. Schepis
- F. Assaderaghi
- et al.
- 1997
- IEDM 1997
On the control of short-channel effect for MOSFETs with reverse halo implantation
- Huilong Zhu
- Huicai Zhong
- et al.
- 2007
- IEEE Electron Device Letters
CMOS compatible high performance IIIV devices: Opportunities and challenges
- Yanning Sun
- Kuen-Ting Shiu
- et al.
- 2016
- ECS Meeting 2016
Synchronized Analog Capacitor Arrays for Parallel Convolutional Neural Network Training
- Effendi Leobandung
- Malte J. Rasch
- et al.
- 2020
- MWSCAS 2020