Advanced Multi-Vt Enabled by Selective Layer Reductions for 2nm Nanosheet Technology and Beyond
- Ruqiang Bao
- Yusuke Oniki
- et al.
- 2024
- IEDM 2024
Publications
Date
Featured collections
Popular topics
63 results for Effendi Leobandung
High Performance Nanosheet Technology Optimized for 77 K
- R. Bao
- L. Qin
- et al.
- 2023
- IEDM 2023
Critical Elements for Next Generation High Performance Computing Nanosheet Technology
- R. Bao
- C. Durfee
- et al.
- 2021
- IEDM 2021
Unassisted true analog neural network training chip
- Y. Kohda
- Y. Li
- et al.
- 2020
- IEDM 2020
High Performance InGaAs Gate-All-Around Nanosheet FET on Si Using Template Assisted Selective Epitaxy
- S. Lee
- Cheng-Wei Cheng
- et al.
- 2018
- IEDM 2018
First demonstration of high-Ge-content strained-Si1-xGex (x=0.5) on insulator PMOS FinFETs with high hole mobility and aggressively scaled fin dimensions and gate lengths for high-performance applications
- Pouya Hashemi
- Karthik Balakrishnan
- et al.
- 2014
- IEDM 2014
High-performance CMOS-compatible self-aligned In0.53Ga0.47As MOSFETs with GMSAT over 2200 μs/μm at VDD = 0.5 v
- Yanning Sun
- Amlan Majumdar
- et al.
- 2014
- IEDM 2014
Self-aligned III-V MOSFETs: Towards a CMOS compatible and manufacturable technology solution
- Y. Sun
- A. Majumdar
- et al.
- 2013
- IEDM 2013
Statistical measurement of random telegraph noise and its impact in scaled-down high-κ/metal-gate MOSFETs
- H. Miki
- N. Tega
- et al.
- 2012
- IEDM 2012
Evaluation methodology for random telegraph noise effects in SRAM arrays
- M. Yamaoka
- Hiroshi Miki
- et al.
- 2011
- IEDM 2011