Electrical integrity of state-of-the-art 0.13 μm SOI CMOS devices and circuits transferred for three-dimensional (3D) integrated circuit (IC) fabrication
- K.W. Guarini
- A. Topol
- et al.
- 2002
- IEDM 2002
Publications
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104 results for David J. Frank
Power-constrained device and technology design for the end of scaling
- David J. Frank
- 2002
- IEDM 2002
25 nm CMOS design considerations
- Y. Taur
- C. Wann
- et al.
- 1998
- IEDM 1998
RF perspective of sub-tenth-micron CMOS
- C. Wann
- L. Su
- et al.
- 1998
- ISSCC 1998
Probing the limits of silicon-based nanoelectronics
- S.J. Wind
- Y. Taur
- et al.
- 1995
- MRS Spring Meeting 1995
Design and performance considerations for sub-0.1 μm double-gate SOI MOSFETs
- H.-S. Wong
- D.J. Frank
- et al.
- 1994
- IEDM 1994
Monte Carlo simulation of a 30 nm dual-gate MOSFET: How short can Si go?
- D.J. Frank
- S.E. Laux
- et al.
- 1992
- IEDM 1992
SELF-ALIGNED PROCESSES FOR THE GaAs GATE FET.
- H. Baratte
- D.C. La Tulipe
- et al.
- 1985
- IEDM 1985
New phenomena in coupled transport between 2D and 3D electron-gas layers
- P. Solomon
- P.J. Price
- et al.
- 1989
- Physical Review Letters
A Simulation Study on Minimizing Threshold Voltage Variability by Optimizing Oxygen Vacancy Concentration under Metal Gate Granularity
- Madhu Padmanabha Sumangala
- Ahish Shylendra
- et al.
- 2020
- IEEE Electron Device Letters