High performance CMOS variability in the 65nm regime and beyond
- Sani Nassif
- Kerry Bernstein
- et al.
- 2007
- IEDM 2007
Publications
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107 results for David J. Frank
35nm SOI-CMOS for sub-ambient temperature operation
- Cai Jin
- David J. Frank
- et al.
- 2007
- VLSI-TSA 2007
Overlay as the key to drive wafer scale 3D integration
- Steven E. Steen
- Douglas LaTulipe
- et al.
- 2007
- Microelectronic Engineering
Critical aspects of layer transfer and alignment tolerances for 3D integration processes
- D.C. La Tulipe
- L.T. Shi
- et al.
- 2006
- GBC 2006
Design and CAD challenges in 45nm CMOS and beyond
- David J. Frank
- Ruchir Puri
- et al.
- 2006
- ICCAD 2006
High-performance CMOS variability in the 65-nm regime and beyond
- Kerry Bernstein
- David J. Frank
- et al.
- 2006
- IBM J. Res. Dev
Optimizing CMOS technology for maximum performance
- David J. Frank
- Wilfried Haensch
- et al.
- 2006
- IBM J. Res. Dev
Three-dimensional integrated circuits
- Anna W. Topol
- Douglas C. La Tulipe Jr.
- et al.
- 2006
- IBM J. Res. Dev
Optimal UTB FD/SOI device structure using thin BOX for sub-50-nm SRAM design
- Saibal Mukhopadhyay
- Keunwoo Kim
- et al.
- 2006
- IEEE Electron Device Letters
Enabling SOI-based assembly technology for three-dimensional (3D) integrated circuits (ICs)
- A. Topol
- D.C. La Tulipe
- et al.
- 2005
- IEDM 2005