New layout dependency in high-k/metal gate MOSFETs
- M. Hamaguchi
- Deleep R. Nair
- et al.
- 2011
- IEDM 2011
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19 results for John Sudijono
Optimizing stressor film deposition sequence in polish rate order for best planarization
- John H. Zhang
- Changyong Xiao
- et al.
- 2011
- MRS Spring Meeting 2011
Competitive and cost effective high-k based 28nm CMOS technology for low power applications
- F. Arnaud
- A. Thean
- et al.
- 2009
- IEDM 2009
32nm general purpose bulk CMOS technology for high performance applications at low voltage
- F. Arnaud
- J. Liu
- et al.
- 2008
- IEDM 2008
Novel enhanced stressor with graded embedded SiGe source/drain for high performance CMOS devices
- J.-P. Han
- H. Utomo
- et al.
- 2006
- IEDM 2006
Dual stress liner for high performance sub-45nm gate length SOI CMOS manufacturing
- H.S. Yang
- R. Malik
- et al.
- 2004
- IEDM 2004
High performance and low power transistors integrated in 65nm bulk CMOS technology
- Z. Luo
- A. Steegen
- et al.
- 2004
- IEDM 2004
High performance bulk planar 20nm CMOS technology for low power mobile applications
- Huiling Shang
- Sameer Jain
- et al.
- 2012
- VLSI Technology 2012
Performance elements for 28nm gate length bulk devices with gate first high-k metal gate
- Jun Yuan
- C. Gruensfelder
- et al.
- 2010
- ICSICT 2010
Critical ultra low-k TDDB reliability issues for advanced CMOS technologies
- F. Chen
- M. Shinosky
- et al.
- 2009
- IRPS 2009