EFFICIENT FAULT SIMULATION OF CMOS CIRCUITS WITH ACCURATE MODELS.
- Z. Barzilai
- J.Lawrence Carter
- et al.
- 1985
- IEEE ITC 1985
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16 results for Indira Nair
Transaction-level modeling for architectural and power analysis of PowerPC and CoreConnect-based systems
- Nagu Dhanwada
- Reinaldo A. Bergamaschi
- et al.
- 2006
- Des Autom Embedded Syst
The effect of dynamic power management on mid-frequency and low-frequency power supply noise
- Howard Chen
- Indira Nair
- et al.
- 2010
- Journal of Low Power Electronics
Early analysis tools for system-on-a-chip design
- J.A. Darringer
- Reinaldo A. Bergamaschi
- et al.
- 2002
- IBM J. Res. Dev
Control-flow versus data-flow-based scheduling: Combining both approaches in an adaptive scheduling system
- Reinaldo A. Bergamaschi
- Salil Raje
- et al.
- 1997
- IEEE Transactions on VLSI Systems
AVPGEN—A Test Generator for Architecture Verification
- A.K. Chandra
- V.S. Iyengar
- et al.
- 1995
- IEEE Transactions on VLSI Systems