AVPGEN—A Test Generator for Architecture Verification
- A.K. Chandra
- V.S. Iyengar
- et al.
- 1995
- IEEE Transactions on VLSI Systems
Publications
Date
Featured collections
Popular topics
16 results for Indira Nair
Architectural verification of processors using symbolic instruction graphs
- A.K. Chandra
- V.S. Iyengar
- et al.
- 1994
- ICCD 1994
Symbolic implication in test generation
- Sandip Kundu
- I. Nair
- et al.
- 1992
- European Conference on Design Automation 1992
A small test generator for large designs
- Sandip Kundu
- Leendert M. Huisman
- et al.
- 1992
- IEEE ITC 1992
Fault simulation on message passing
- Leendert M. Huisman
- Raja Daoud
- et al.
- 1990
- DMCC 1990
EFFICIENT FAULT SIMULATION OF CMOS CIRCUITS WITH ACCURATE MODELS.
- Z. Barzilai
- J.Lawrence Carter
- et al.
- 1985
- IEEE ITC 1985