Combined C-V/I-V front-end-of-line measurement
- Stas Polonsky
- Simeon Realov
- et al.
- 2012
- ICMTS 2012
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19 results for Michael Hargrove
A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications
- S. Krishnan
- U. Kwon
- et al.
- 2011
- IEDM 2011
Gate length scaling and high drive currents enabled for high performance SOI technology using high-κ/metal gate
- K. Henson
- H. Bu
- et al.
- 2008
- IEDM 2008
Characterization of fast relaxation during BTI stress in conventional and advanced CMOS devices with HfO2 gate stacks
- Andreas Kerber
- Kingsuk Maitra
- et al.
- 2008
- IEEE Transactions on Electron Devices
High-performance high-κ/metal gates for 45nm CMOS and beyond with gate-first processing
- M. Chudzik
- B. Doris
- et al.
- 2007
- VLSI Technology 2007
High performance 45-nm SOI technology with enhanced strain, porous low-k BEOL, and immersion lithography
- S. Narasimha
- K. Onishi
- et al.
- 2006
- IEDM 2006
Effect of thermal processing on strain relaxation and interdiffusion in Si/SiGe heterostructures studied using Raman spectroscopy
- S.J. Koester
- K. Rim
- et al.
- 2001
- Applied Physics Letters
Strained Si NMOSFETs for high performance CMOS technology
- K. Rim
- S.J. Koester
- et al.
- 2001
- VLSI Technology 2001
High performance 0.13 μm SOI CMOS technology with Cu interconnects and low-k BEOL dielectric
- P. Smeys
- V. McGahay
- et al.
- 2000
- VLSI Technology 2000
RF potential of a 0.18-μm CMOS logic device technology
- Joachim N. Burghartz
- Michael Hargrove
- et al.
- 2000
- IEEE Transactions on Electron Devices