Trimming of hard-masks by gaseous chemical oxide removal (COR) for sub-10nm gates/fins, for gate length control and for embedded logic
- Wesley C. Natzle
- David Horak
- et al.
- 2004
- ASMC 2004
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13 results for Sadanand Deshpande
Device Design Considerations for Ultra-Thin SOI MOSFETs
- B. Doris
- M. Ieong
- et al.
- 2003
- IEDM 2003
A high performance 90 nm SOI technology with 0.992 μm2 6T-SRAM cell
- Mukesh Khare
- S. Ku
- et al.
- 2002
- IEDM 2002