Publications

10 results for James O'Neill

ETSOI CMOS for system-on-chip applications featuring 22nm gate length, sub-100nm gate pitch, and 0.08μm² SRAM cell
- - Kangguo Cheng
  - A. Khakifirooz
  - et al.
- 2011
- VLSI Circuits 2011
Sub-25nm FinFET with advanced fin formation and short channel effect engineering
- - Tenko Yamashita
  - Veeraraghvan S. Basker
  - et al.
- 2011
- VLSI Technology 2011
ETSOI CMOS for system-on-chip applications featuring 22nm gate length, sub-100nm gate pitch, and 0.08μm² SRAM cell
- - Kangguo Cheng
  - A. Khakifirooz
  - et al.
- 2011
- VLSI Technology 2011
Opportunities and challenges of FinFET as a device structure candidate for 14nm node CMOS technology
- - Tenko Yamashita
  - Veeraraghvan S. Basker
  - et al.
- 2011
- CSTIC 2011
Extremely thin SOI (ETSOI) technology: Past, present, and future
- - Kangguo Cheng
  - A. Khakifirooz
  - et al.
- 2010
- IEEE International SOI Conference 2010
Challenges and opportunities of extremely thin SOI (ETSOI) CMOS technology for future low power and general purpose system-on-chip applications
- - A. Khakifirooz
  - Kangguo Cheng
  - et al.
- 2010
- VLSI-TSA 2010
A 0.063 μm² FinFET SRAM cell demonstration with conventional lithography using a novel integration scheme with aggressively scaled fin and gate pitch
- - Veeraraghvan S. Basker
  - Theodorus E. Standaert
  - et al.
- 2010
- VLSI Technology 2010
Challenges and solutions of FinFET integration in an SRAM cell and a logic circuit for 22 nm node and beyond
- - H. Kawasaki
  - V.S. Basker
  - et al.
- 2009
- IEDM 2009
Extremely thin SOI (ETSOI) CMOS with record low variability for low power system-on-chip applications
- - K. Cheng
  - A. Khakifirooz
  - et al.
- 2009
- IEDM 2009
Fully depleted extremely thin SOI technology fabricated by a novel integration scheme featuring implant-free, zero-silicon-loss, and faceted raised source/drain
- - K. Cheng
  - A. Khakifirooz
  - et al.
- 2009
- VLSI Technology 2009