A 32kb 10T subthreshold SRAM array with bit-interleaving and differential read scheme in 90nm CMOSIk Joon ChangJae-Joon Kimet al.2008ISSCC 2008
Column-selection-enabled 8T SRAM array with 1R/1W multi-port operation for DVFS-enabled processorsSang Phill ParkSoo Youn Kimet al.2011ISLPED 2011
A 32 kb 10T sub-threshold sram array with bit-interleaving and differential read scheme in 90 nm CMOSIk Joon ChangJae-Joon Kimet al.2009IEEE Journal of Solid-State Circuits