Spacer-defined double patterning for 20-nm and beyond logic BEOL technology
- Ryoung-Han Kim
- Chiew-Seng Koay
- et al.
- 2011
- SPIE Advanced Lithography 2011
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6 results for Harry J. Levinson
Spacer defined double patterning for sub-72 nm pitch logic technology
- Ryoung-Han Kim
- Erin McLellan
- et al.
- 2010
- SPIE Advanced Lithography 2010
Exposure tool settings and OPC strategies for EUV Lithography at the 16nm node
- Yunfei Deng
- Jongwook Kye
- et al.
- 2009
- SPIE Advanced Lithography 2009
22 nm technology node active layer patterning for planar transistor devices
- Ryoung-Han Kim
- Steven Holmes
- et al.
- 2009
- SPIE Advanced Lithography 2009
A year in the life of an immersion lithography alpha tool at albany NanoTech
- Michael Tittnich
- John Hartley
- et al.
- 2006
- SPIE Advanced Lithography 2006
22-nm-node technology active-layer patterning for planar transistor devices
- Ryoung-Han Kim
- Steven Holmes
- et al.
- 2010
- J. Micro/Nanolithogr. MEMS MOEMS