High-performance three-dimensional on-chip inductors in SOI CMOS technology for monolithic RF circuit applications
- Jonghae Kim
- Jean-Olivier Plouchart
- et al.
- 2003
- IMS 2003
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34 results for M. Sherony
Suitability of scaled SOI CMOS for high-frequency analog circuits
- N. Zamdmer
- J.O. Plouchart
- et al.
- 2002
- ESSDERC 2002
Effects of gate-to-body tunneling current on PD/SOI CMOS SRAM
- R.V. Joshi
- C.T. Chuang
- et al.
- 2001
- VLSI Technology 2001
Silicon-on-insulator dynamic threshold ESD networks and active clamp circuitry
- S. Voldman
- D. Hui
- et al.
- 2000
- EOS/ESD 2000
Design of a high performance PD SOI for the 0.18 μm technology generation
- M. Sherony
- S.-H. Lo
- et al.
- 2000
- ICM 2000
Partially depleted silicon-on-insulator (SOI): A device design/modeling and circuit perspective
- F. Assaderaghi
- G. Shahidi
- et al.
- 2000
- ICM 2000
Partially-depleted SOI compact model - formulation and parameter extraction
- S.K.H. Fung
- L. Wagner
- et al.
- 2000
- VLSI Technology 2000
Electrostatic discharge protection in silicon-on-insulator technology
- S. Voldman
- D. Hui
- et al.
- 1999
- IEEE International SOI Conference 1999
Self-annealing effect of tensile liner on thick-Tinv PMOS
- Qintao Zhang
- Jie Chen
- et al.
- 2011
- IEEE T-ED
Novel high-performance analog devices for advanced low-power high-k metal gate complementary metal-oxide-semiconductor technology
- Jin-Ping Han
- Takashi Shimizu
- et al.
- 2011
- Japanese Journal of Applied Physics