A 12-to-26GHz fractional-N PLL with dual continuous tuning LC-D/VCOs
- Mark Ferriss
- Bodhisatwa Sadhu
- et al.
- 2016
- ISSCC 2016
Publications
Date
Featured collections
Popular topics
27 results for Mark Ferriss
A 13.1-to-28GHz fractional-N PLL in 32nm SOI CMOS with a ΔΣ noise-cancellation scheme
- Mark Ferriss
- Bodhisatwa Sadhu
- et al.
- 2015
- ISSCC 2015
A 250-mW 60-GHz CMOS Transceiver SoC Integrated with a Four-Element AiP Providing Broad Angular Link Coverage
- Bodhisatwa Sadhu
- Alberto Valdes-Garcia
- et al.
- 2020
- IEEE JSSC
A 28-GHz 32-Element TRX Phased-Array IC with Concurrent Dual-Polarized Operation and Orthogonal Phase and Gain Control for 5G Communications
- Bodhisatwa Sadhu
- Yahya Tousi
- et al.
- 2017
- IEEE JSSC
A 1.4 pJ/bit, Power-Scalable 16×12 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology
- Timothy O. Dickson
- Yong Liu
- et al.
- 2015
- IEEE JSSC
A 52 GHz frequency synthesizer featuring a 2nd harmonic extraction technique that preserves VCO performance
- Bodhisatwa Sadhu
- Mark Ferriss
- et al.
- 2015
- IEEE JSSC
A 28 GHz hybrid PLL in 32 nm SOI CMOS
- Mark Ferriss
- Alexander Rylyakov
- et al.
- 2014
- IEEE JSSC
A linearized, low-phase-noise VCO-based 25-GHz PLL with autonomic biasing
- Bodhisatwa Sadhu
- Mark A. Ferriss
- et al.
- 2013
- IEEE JSSC
An integral path self-calibration scheme for a dual-loop PLL
- Mark Ferriss
- Jean-Olivier Plouchart
- et al.
- 2013
- IEEE JSSC
A Software-Defined Phased Array Radio with mmWave to Software Vertical Stack Integration for 5G Experimentation
- Bodhisatwa Sadhu
- Arun Paidimarri
- et al.
- 2018
- IMS 2018