Publications

3 results for Anthony Pelella

A 6+ Ghz 128Kb Multi-Port L1 Cache Using Ground Rule Clean 10T Bitcells in 5Nm Technology
- - Rajiv Joshi
  - John Davis
  - et al.
- 2025
- VLSI Technology and Circuits 2025
The dawn of predictive chip yield design: Along and beyond the memory lane
- - Rajiv Joshi
  - Rouwaida Kanj
  - et al.
- 2010
- IEEE Design and Test of Computers
Evaluation and alleviation of SOI impacts on SRAM functionality and yield
- - Antonio R. Pelella
  - Rajiv Joshi
  - et al.
- 2008
- IEEE International SOI Conference 2008