A 6+ GHz 128KB Multi-Port L1 Cache using Ground Rule Clean 10T Bitcells in 5nm Technology

A 6+ GHz multi-port 10T Ground Rule Clean (GRC) compact Cache is implemented in the recently announced IBM Telum II processor [1]. It features a Multi port design (2 Read and 1 Write) with fine grain banked architecture minimizing read and write collisions. The design is functional across various corner conditions without read and write assist circuits.