Electrical test strategies for a wafer-level packaging technology
- David C. Keezer
- Chirag S. Patel
- et al.
- 2003
- IEEE Transactions on Electronics Packaging Manufacturing
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20 results for James D. Meindl
Sea of leads (SoL) ultrahigh density wafer-level chip input/output interconnections for gigascale integration (GSI)
- Muhannad S. Bakir
- Hollie A. Reed
- et al.
- 2003
- IEEE Transactions on Electron Devices
Interconnect opportunities for gigascale integration
- James D. Meindl
- Jeffrey A. Davis
- et al.
- 2002
- IBM J. Res. Dev
Device parameter optimization for reduced short channel effects in retrograde doping MOSFET
- Bhavna Agrawal
- K. De Vivek
- et al.
- 1996
- IEEE Transactions on Electron Devices
Analysis, Design, and Performance of a Capacitive Pressure Sensor IC
- Michael J. S. Smith
- Lyn Bowman
- et al.
- 1986
- IEEE T-BME
Performance Limits of CMOS ULSI
- James R. Pfiester
- John D. Shott
- et al.
- 1985
- IEEE Journal of Solid-State Circuits
Performance Limits of CMOS ULSI
- James R. Pfiester
- John D. Shott
- et al.
- 1985
- IEEE T-ED
A Conduction Model for Semiconductor–Grain-Boundary-Semiconductor Barriers in Polycrystalline-Silicon Films
- Nicky Chau-Chun Lu
- Chih-Yuan Lu
- et al.
- 1983
- IEEE T-ED
Scaling Limitations of Monolithic Polycrystalline-Silicon Resistors in VLSI Static RAM's and Logic
- Levy Gerzberg
- James D. Meindl
- 1982
- IEEE Journal of Solid-State Circuits
Scaling Limitations of Monolithic Polycrystalline-Silicon Resistors in VLSI Static RAM's and Logic
- Nicky Chau-Chun Lu
- Levy Gerzberg
- et al.
- 1982
- IEEE T-ED