Subtractive Ru Interconnect Enabled by Novel Patterning Solution for EUV Double Patterning and TopVia with Embedded Airgap Integration for Post Cu Interconnect Scaling
- C. J. Penny
- Koichi Motoyama
- et al.
- 2022
- IEDM 2022
Publications
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84 results for Lawrence Clevenger
System Performance: From Enterprise to AI
- Arvind Kumar
- Leland Chang
- et al.
- 2018
- IEDM 2018
Fully aligned via integration for extendibility of interconnects to beyond the 7 nm node
- Benjamin D. Briggs
- C.B. Peethala
- et al.
- 2017
- IEDM 2017
CMOS compatible MIM decoupling capacitor with reliable sub-nm EOT high-k stacks for the 7 nm node and beyond
- Takashi Ando
- Eduard Cartier
- et al.
- 2016
- IEDM 2016
High performance 14nm SOI FinFET CMOS technology with 0.0174μm2 embedded DRAM and 15 levels of Cu metallization
- C.-H.C-H. Lin
- Brian Greene
- et al.
- 2014
- IEDM 2014
High reliability 32 nm Cu/ULK BEOL based on PVD CuMn seed, and its extendibility
- Takeshi Nogami
- Tibor Bolom
- et al.
- 2010
- IEDM 2010
A 45 nm CMOS node Cu/low-k/ ULtra low-k PECVD SiCOH (k=2.4) BEOL technology
- S. Sankaran
- S. Arai
- et al.
- 2006
- IEDM 2006
Surface roughening during titanium silicide formation: A comparison between Si(100) and poly-Si substrates
- C. Lavoie
- R. Martel
- et al.
- 1996
- MRS Fall Meeting 1996
In-situ X-ray diffraction analysis of TiSi2 phase formation from a titanium-molybdenum bilayer
- C. Cabral Jr.
- L. Clevenger
- et al.
- 1996
- MRS Fall Meeting 1996
In situ TEM analysis of TiSi2 C49-C54 transformations during annealing
- L. Gignac
- V. Svilan
- et al.
- 1996
- MRS Fall Meeting 1996