Distributed Network of LDO Microregulators Providing Submicrosecond DVFS and IR Drop Compensation for a 24-Core Microprocessor in 14-nm SOI CMOS
- Miguel E. Perez
- Michael A. Sperling
- et al.
- 2020
- IEEE JSSC
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6 results for Michael A. Sperling
The 12-core POWER8™ processor with 7.6 Tb/s IO bandwidth, integrated voltage regulation, and resonant clocking
- Eric J. Fluhr
- Steve Baumgartner
- et al.
- 2015
- IEEE JSSC
Distributed Network of LDO Microregulators Providing Submicrosecond DVFS and IR Drop Compensation for a 24-Core Microprocessor in 14nm SOI CMOS
- Miguel E. Perez
- Michael A. Sperling
- et al.
- 2019
- CICC 2019
A DPLL-based per core variable frequency clock generator for an eight-core POWER7™ microprocessor
- Jose Tierno
- Alexander Rylyakov
- et al.
- 2010
- VLSI Circuits 2010
A wide tuning range (1 GHz-to-15 GHz) fractional-N all-digital PLL in 45nm SOI
- Alexander Rylyakov
- Jose Tierno
- et al.
- 2008
- CICC 2008
A 45 nm SOI embedded DRAM macro for the POWER™ processor 32 MByte on-chip L3 cache
- John Barth
- Don Plass
- et al.
- 2011
- IEEE Journal of Solid-State Circuits