Eric J. Fluhr, Joshua Friedrich, et al.
ISSCC 2014
POWER8™ is a 12-core processor fabricated in IBM's 22 nm SOI technology with core and cache improvements driven by big data applications, providing 2.5× socket performance over POWER7+™. Core throughput is supported by 7.6 Tb/s of off-chip I/O bandwidth which is provided by three primary interfaces, including two new variants of Elastic Interface as well as embedded PCI Gen-3. Power efficiency is improved with several techniques. An on-chip controller based on an embedded PowerPC™ 405 processor applies per-core DVFS by adjusting DPLLs and fully integrated voltage regulators. Each voltage regulator is a highly distributed system of digitally controlled microregulators, which achieves a peak power efficiency of 90.5%. A wide frequency range resonant clock design is used in 13 clock meshes and demonstrates a minimum power savings of 4%. Power and delay efficiency is achieved through the use of pulsed-clock latches, which require statistical validation to ensure robust yield.
Eric J. Fluhr, Joshua Friedrich, et al.
ISSCC 2014
Eric J. Fluhr, R.M. Rao, et al.
IBM J. Res. Dev
Fadi H. Gebara, Jeremy D. Schaub, et al.
ISSCC 2007
Joshua Friedrich, Hung Le, et al.
ICICDT 2014