Design techniques for CMOS backplane transceivers approaching 30-Gb/s data rates
- John F. Bulzacchelli
- 2013
- CICC 2013
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63 results for John F. Bulzacchelli
Direct measurement of jitter in a JTL
- Y.-K.-K. Fung
- G.W. Gibson
- et al.
- 2013
- IEEE TAS
Root cause identification of an hard-to-find on-chip power supply coupling fail
- Franco Stellari
- Thomas Cowell
- et al.
- 2012
- IEEE ITC 2012
A 28-Gb/s 4-Tap FFE/15-Tap DFE Serial Link Transceiver in 32-nm SOI CMOS Technology
- John F. Bulzacchelli
- Christian Menolfi
- et al.
- 2012
- IEEE JSSC
A 16-Gb/s backplane transceiver with 12-tap current integrating DFE and dynamic adaptation of voltage offset and timing driftsin 45-nm SOI CMOS technology
- Gautam R. Gangasani
- Chun-Ming Hsu
- et al.
- 2012
- IEEE JSSC
A 28Gb/s 4-tap FFE/15-tap DFE serial link transceiver in 32nm SOI CMOS technology
- John Bulzacchelli
- Troy Beukema
- et al.
- 2012
- ISSCC 2012
A 19Gb/s serial link receiver with both 4-tap FFE and 5-tap DFE functions in 45nm SOI CMOS
- Ankur Agrawal
- John Bulzacchelli
- et al.
- 2012
- ISSCC 2012
An 8x 10-Gb/s source-synchronous I/O system based on high-density silicon carrier interconnects
- Timothy O. Dickson
- Yong Liu
- et al.
- 2012
- IEEE Journal of Solid-State Circuits
Dual-loop system of distributed microregulators with high DC accuracy, load response time below 500 ps, and 85-mV dropout voltage
- John F. Bulzacchelli
- Zeynep Toprak-Deniz
- et al.
- 2012
- IEEE Journal of Solid-State Circuits
A 16-Gb/s backplane transceiver with 12-tap current integrating DFE and dynamic adaptation of voltage offset and timing drifts in 45-nm SOI CMOS technology
- Gautam R. Gangasani
- Chun-Ming Hsu
- et al.
- 2011
- CICC 2011