A 25 Gb/s burst-mode receiver for low latency photonic switch networks
- Alexander V. Rylyakov
- Jonathan E. Proesel
- et al.
- 2015
- OFC 2015
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60 results for John F. Bulzacchelli
A 1.4-pJ/b, power-scalable 16×12-Gb/s source-synchronous I/O with DFE receiver in 32nm SOI CMOS technology
- Timothy O. Dickson
- Yong Liu
- et al.
- 2014
- CICC 2014
A 32-Gb/s backplane transceiver with on-chip AC-coupling and low latency CDR in 32-nm SOI CMOS technology
- Gautam R. Gangasani
- John F. Bulzacchelli
- et al.
- 2013
- A-SSCC 2013
Design techniques for CMOS backplane transceivers approaching 30-Gb/s data rates
- John F. Bulzacchelli
- 2013
- CICC 2013
Root cause identification of an hard-to-find on-chip power supply coupling fail
- Franco Stellari
- Thomas Cowell
- et al.
- 2012
- IEEE ITC 2012
A 16-Gb/s backplane transceiver with 12-tap current integrating DFE and dynamic adaptation of voltage offset and timing drifts in 45-nm SOI CMOS technology
- Gautam R. Gangasani
- Chun-Ming Hsu
- et al.
- 2011
- CICC 2011
Dual-loop system of distributed microregulators with high DC accuracy, load response time below 500ps, and 85mV dropout voltage
- Zeynep Toprak-Deniz
- John Bulzacchelli
- et al.
- 2011
- VLSI Circuits 2011
An 8x10-Gb/s source-synchronous I/O system based on high-density silicon carrier interconnects
- Timothy O. Dickson
- Yong Liu
- et al.
- 2011
- VLSI Circuits 2011
A 7.5-GS/s 3.8-ENOB 52-mW flash ADC with clock duty cycle control in 65nm CMOS
- Hayun Chung
- Alexander Rylyakov
- et al.
- 2009
- VLSI Circuits 2009
A 12-Gb/s 11-mW half-rate sampled 5-tap decision feedback equalizer with current-integrating summers in 45-nm SOI CMOS technology
- Timothy O. Dickson
- John F. Bulzacchelli
- et al.
- 2008
- VLSI Circuits 2008