Power-aware microarchitecture: Design and modeling challenges for next-generation microprocessors
- David M. Brooks
- Pradip Bose
- et al.
- 2000
- IEEE Micro
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28 results for S.E. Schuster
CMOS circuit technology for sub-ambient temperature operation
- I. Aller
- K. Bernstein
- et al.
- 2000
- Digest of Technical Papers - IEEE International Solid-State Circuits Conference
A 2-ns Cycle, 3.8-ns Access 512-kb CMOS ECL SRAM with a Fully Pipelined Architecture
- Terry I. Chappell
- Barbara A. Chappell
- et al.
- 1991
- IEEE Journal of Solid-State Circuits
A 3.5-ns/77 K and 6.2-ns/300 K 64K CMOS RAM with ECL Interfaces
- Terry I. Chappell
- Stanley E. Schuster
- et al.
- 1989
- IEEE Journal of Solid-State Circuits
Fast CMOS ECL Receivers with 100-mV Worst-Case Sensitivity
- Barbara A. Chappell
- Terry I. Chappell
- et al.
- 1988
- IEEE Journal of Solid-State Circuits
Stability and SER Analysis of Static RAM Cells
- Barbara Chappell
- Stanley E. Schuster
- et al.
- 1985
- IEEE Journal of Solid-State Circuits
A 20 ns 64K (4K X16) NMOS RAM
- Stanley E. Schuster
- Barbara Chappell
- et al.
- 1984
- IEEE Journal of Solid-State Circuits
1 μm MOSFET VLSI Technology: Part Ill—Logic Circuit Design Methodology and Applications
- Peter W. Cook
- Stanley E. Schuster
- et al.
- 1979
- IEEE T-ED