Fast low power eDRAM hierarchical differential sense amplifier
- Stanley E. Schuster
- Richard E. Matick
- 2009
- IEEE Journal of Solid-State Circuits
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28 results for S.E. Schuster
Connections and disconnections on integrated circuits using nanosecond laser pulses
- P.W. Cook
- S.E. Schuster
- et al.
- 2008
- Applied Physics Letters
A 500 MHz Random Cycle, 1.5 ns Latency, SOI Embedded DRAM Macro Featuring a Three-Transistor Micro Sense Amplifier
- John Barth
- William R. Reohr
- et al.
- 2008
- IEEE Journal of Solid-State Circuits
A 500MHz random cycle 1.5ns-latency, SOI embedded DRAM macro featuring a 3T micro sense amplifier
- John Barth
- William Reohr
- et al.
- 2007
- ISSCC 2007
Logic-based eDRAM: Origins and rationale for use
- Richard E. Matick
- Stanley E. Schuster
- 2005
- IBM J. Res. Dev
Low-power synchronous-to-asynchronous-to-synchronous interlocked pipelined CMOS circuits operating at 3.3-4.5 GHz
- Stanley E. Schuster
- Peter W. Cook
- 2003
- IEEE Journal of Solid-State Circuits
Tradeoffs in power-efficient issue queue design
- Alper Buyuktosunoglu
- David H. Albonesi
- et al.
- 2002
- LPED 2002
Synchronous interlocked pipelines
- Hans M. Jacobson
- Prabhakar N. Kudva
- et al.
- 2002
- ASYNC 2002
Asynchronous interlocked pipelined CMOS circuits operating at 3.3-4.5Ghz
- S.E. Schuster
- W. Reohr
- et al.
- 2000
- ISSCC 2000
Power-aware microarchitecture: Design and modeling challenges for next-generation microprocessors
- David M. Brooks
- Pradip Bose
- et al.
- 2000
- IEEE Micro