A 500MHz random cycle 1.5ns-latency, SOI embedded DRAM macro featuring a 3T micro sense amplifier
- John Barth
- William Reohr
- et al.
- 2007
- ISSCC 2007
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28 results for S.E. Schuster
Asynchronous interlocked pipelined CMOS circuits operating at 3.3-4.5Ghz
- S.E. Schuster
- W. Reohr
- et al.
- 2000
- ISSCC 2000
SOI for a 1-Volt CMOS Technology and Application to a 512kb SRAM with 3.5 ns Access Time
- G. Shahidi
- T.H. Ning
- et al.
- 1993
- IEDM 1993
1 µm MOSFET VLSI Technology: Part III-Logic Circuit Design Methodology and Applications
- Darryl R. Freedman
- Stanley E. Schuster
- et al.
- 1979
- IEEE JSSC
1, μm MOSFET VLSI Technology: Part IV-Hot-Electron Design Constraints
- Tak H. Ning
- Peter W. Cook
- et al.
- 1979
- IEEE JSSC
A Study in the Use of PLA-Based Macros
- Peter W. Cook
- Chung W. Ho
- et al.
- 1979
- IEEE JSSC
Multiple Word/Bit Line Redundancy for Semiconductor Memories
- Stanley E. Schuster
- 1978
- IEEE JSSC
Experimental Study of Laser Formed Connections for LSI Wafer Personalization
- Lawrence Kuhn
- Stanley E. Schuster
- et al.
- 1975
- IEEE JSSC
Tradeoffs in power-efficient issue queue design
- Alper Buyuktosunoglu
- David H. Albonesi
- et al.
- 2002
- LPED 2002
Synchronous interlocked pipelines
- Hans M. Jacobson
- Prabhakar N. Kudva
- et al.
- 2002
- ASYNC 2002