CMOS scaling into the nanometer regime
- Yuan Taur
- Douglas A. Buchanan
- et al.
- 1997
- Proceedings of the IEEE
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46 results for G.A. Sai-Halasz
CMOS scaling into the 21st century: 0.1 μm and beyond
- Y. Taur
- Y. Mii
- et al.
- 1995
- IBM J. Res. Dev
Performance Trends in High-End Processors
- George A. Sai-Halasz
- 1995
- Proceedings of the IEEE
VLSI on-chip interconnection performance simulations and measurements
- D. Edelstein
- G.A. Sai-Halasz
- et al.
- 1995
- IBM J. Res. Dev
Shallow p+ junction formation by a reverse-type dopant preamorphization scheme
- E. Ganin
- B. Davari
- et al.
- 1989
- Applied Physics Letters
New preamorphization technique for very shallow p+-n junctions
- B. Davari
- E. Ganin
- et al.
- 1989
- VLSI Technology 1989
Inverter Performance Of Deep-Submicrometer Mosfet'S
- George A. Sai-Halasz
- Matthew R. Wordeman
- et al.
- 1988
- IEEE Electron Device Letters
High Transconductance and Velocity Overshoot in NMOS Devices at the 0.1-μm Gate-Length Level
- George A. Sai-Halasz
- Matthew R. Wordeman
- et al.
- 1988
- IEEE Electron Device Letters
EXPERIMENTAL TECHNOLOGY AND CHARACTERIZATION OF SELF-ALIGNED 0. 1 mu M-GATE-LENGTH LOW-TEMPERATURE OPERATION NMOS DEVICES.
- G.A. Sai-Halasz
- M.R. Wordeman
- et al.
- 1986
- IEDM 1986
Processing and characterization of ultra-small silicon devices
- G.A. Sai-Halasz
- 1987
- ESSDERC 1987