Dual-loop system of distributed microregulators with high DC accuracy, load response time below 500 ps, and 85-mV dropout voltage
- John F. Bulzacchelli
- Zeynep Toprak-Deniz
- et al.
- 2012
- IEEE Journal of Solid-State Circuits
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Exploiting combinatorial redundancy for offset calibration in flash ADCs
- Gokce Keskin
- Jonathan Proesel
- et al.
- 2011
- IEEE Journal of Solid-State Circuits
A fully-integrated 16-element phased-array receiver in SiGe BiCMOS for 60-GHz communications
- Arun Natarajan
- Scott K. Reynolds
- et al.
- 2011
- IEEE Journal of Solid-State Circuits
POWER7™, a highly parallel, scalable multi-core high end server processor
- Dieter F. Wendel
- Ron Kalla
- et al.
- 2011
- IEEE Journal of Solid-State Circuits
A 45 nm SOI embedded DRAM macro for the POWER™ processor 32 MByte on-chip L3 cache
- John Barth
- Don Plass
- et al.
- 2011
- IEEE Journal of Solid-State Circuits
A 4.5 mW/Gb/s 6.4 Gb/s 22+1-lane source synchronous receiver core with optional cleanup PLL in 65 nm CMOS
- Robert Reutemann
- Michael Ruegg
- et al.
- 2010
- IEEE Journal of Solid-State Circuits
A fully integrated 16-element phased-array transmitter in SiGe BiCMOS for 60-GHz communications
- Alberto Valdes-Garcia
- Sean T. Nicolson
- et al.
- 2010
- IEEE Journal of Solid-State Circuits
A 10-Gb/s compact low-power serial I/O with DFE-IIR equalization in 65-nm CMOS
- Byungsub Kim
- Yong Liu
- et al.
- 2009
- IEEE Journal of Solid-State Circuits
Large-scale SRAM variability characterization in 45 nm CMOS
- Zheng Guo
- Andrew Carlson
- et al.
- 2009
- IEEE Journal of Solid-State Circuits
A 1.255 GHz clock generator with high-bandwidth supply-rejection using a regulated-replica regulator in 45-nm CMOS
- Thomas Toifl
- Christian Menolfi
- et al.
- 2009
- IEEE Journal of Solid-State Circuits