A Circuit Concept for Reducing Soft Error in Highspeed Memory Cells
- Denny D. Tang
- Ching-Te Chuang
- 1988
- IEEE Journal of Solid-State Circuits
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224 results at IEEE Journal of Solid-State Circuits
A 20-ns 128-Kbit X 4 High-Speed DRAM with 330-Mbit/s Data Rate
- Nicky C.C. Lu
- Hu H. Chao
- et al.
- 1988
- IEEE Journal of Solid-State Circuits
Highspeed Sensing Scheme for CMOS DRAM's
- Sang H. Dhong
- Nicky Chau-Chun Lu
- et al.
- 1988
- IEEE Journal of Solid-State Circuits
Fast CMOS ECL Receivers with 100-mV Worst-Case Sensitivity
- Barbara A. Chappell
- Terry I. Chappell
- et al.
- 1988
- IEEE Journal of Solid-State Circuits
High-Speed Operation of Upward-Injecting Transistors by Reducing the Stored Charge
- George C. Feth
- 1987
- IEEE Journal of Solid-State Circuits
Characteristics of a Set of 12.7-mm Processor Chips
- Klaus Klein
- Gunther Koetzle
- et al.
- 1987
- IEEE Journal of Solid-State Circuits
Open-Loop Gain Limitations for Push—Pull Off-Chip Drivers
- Norman Raver
- 1987
- IEEE Journal of Solid-State Circuits
Design Considerations of Dense Bipolar PLA's
- Denny D. Tang
- R.E. Burger
- 1987
- IEEE Journal of Solid-State Circuits
Micro/370: A 32-bit Single-Chip Microprocessor
- Hu H. Chao
- Feng-Hsien W. Shih
- et al.
- 1986
- IEEE Journal of Solid-State Circuits
A 1.0-ns 5-kbit ecl RAM
- Ching-Te Chuang
- Denny D. Tang
- et al.
- 1986
- IEEE Journal of Solid-State Circuits